1. Field of the Invention
The present invention relates to a method of making thin film transistors, and more particularly to a method of making thin film transistors suitable in forming a high quality of thin film transistors-liquid crystal displays in a large area.
2. Description of the Prior Art
Currently, a thin film transistor-liquid crystal display (TFT-LCD) is known as one of the promising flat displays required for obtaining a larger displaying area, a higher pixel density and a better video quality. FIG. 1 shows an equivalent circuit for one pixel in such a TFT-LCD.
Supplying of voltage to each pixel electrode is carried out via a signal line by a corresponding thin film transistor which is switched by a gate voltage supplied via a gate bus line. Generally, a parasitic capacitance (Cgd) is inevitably present between a gate and a drain of the transistor. Accompanying a variation of the gate voltage Vg from a voltage level at ON-state to a voltage level at OFF-state, the parasitic capacitance Cgd causes a feed-through of the pixel electrode voltage, as shown in FIG. 1.
This feed-through voltage V can be expressed by the following formula 1: ##EQU1## where, Cic and Cst are other parasitic capacitances.
The feed-through voltage V acts to break the balance of the voltage applied to the liquid crystal, resulting in flickering of the LCD and a decrease in the reliability. For removing the feed-through voltage, the Cst should be sufficiently large, as compared with the Cgd. When the TFT-LCD has a larger size and a higher pixel density, the Cic increases and the charging time decreases. Accordingly, charging for the enlarged Cic should be in a shortened charging time. Also, the value of W/L (where, W is the channel width of TFT and L is the channel length of TFT) should be increased, which determines the value of ON current for TFT, where L is constant, W and Cgd increase. For effectively removing the feed-through voltage V, the Cst should be increased more. However, the resistance for a SC line can not be decreased to a small value. This is because of a limitation on pixel aperture rate. As a result, it is difficult to control the SC electrode voltage at a larger size of the display. To decrease the Cgd is the most efficient method for solving this problem. The generation of the Cgd results from an overlap between the gate electrode and the source/drain electrodes. However, this overlap is necessarily present in case of an inverted staggered type TFT and can not be reduced below 2 .mu.m due to an accuracy in mask alignment required for a large size of the display.
Referring to FIG. 2, there is illustrated a general inverted staggered type TFT which is characterized by an insulation layer and a semiconductor layer formed on a gate electrode. In such a construction, the overlap can be extremely reduced by self-aligning the source/drain electrodes with the gate electrode. However, known methods use a conventional lift-off process which has no utility for a TFT array.
For solving this problem, a new type of self-aligned TFT has been proposed by S. Nishida et al., Japan NEC corporation. Such a self-aligned TFT is manufactured by using a back substrate exposure process as well as an ion doping process and a chromium silicide formation technique. The self-aligned TFT has a sufficient utility for the manufacture of TFT-LCDs.
Now, a method of making the self-aligned TFT proposed by S. Nishida et al. will be described in conjunction with FIGS. 3a to 3e.
As shown in FIG. 3a, first, on an insulating transparent substrate 1 is formed a gate electrode 2. Over the entire exposed surface of the transparent substrate 1 and gate electrode 2 are deposited a first insulation layer 3, an amorphous silicon layer 4 as a semiconductor layer, and a second insulation layer 5, in this order. A photoresist 6 is subsequently coated over the second insulation layer 5. Thereafter, the photoresist 6 is subjected to a back substrate exposure which is carried out at the back side of the transparent substrate 1, so as to form a photoresist pattern 6a, as shown in FIG. 3b.
The second insulation layer 5 is subsequently subjected to a dry etch using the photoresist pattern 6a as a mask so that it is removed except for its portion disposed beneath the photoresist pattern 6a, so as to form a second insulation layer pattern 5a, as shown in FIG. 3c. Thereafter, the photoresist pattern 6a is removed.
Using the second insulation layer pattern 5a as a mask, high concentration N type (N.sup.+ type) impurity ions such as phosphorous are implanted to a predetermined depth in the amorphous silicon layer 4, with an energy of 30 Kev. Accordingly, the portions of amorphous silicon layer 4 implanted with N.sup.+ type impurity ions form N.sup.+ type conductive layers 7 and 7a which are disposed at opposite sides of the second insulation layer pattern 5a, respectively. At this time, the portion of amorphous silicon layer 4 disposed beneath the second insulation layer pattern 5a is not implanted with the N.sup.+ type impurity ions such as phosphorous.
Over the resultant entire exposed surface, thereafter, a refractory metal layer 8 having a high meting point is deposited using a sputtering process, to have a thickness of 100 nm, as shown in FIG. 3d. Chromium is generally used as the material of refractory metal layer 8. Upon depositing the refractory metal layer 8, the portions of N.sup.+ type conductive layers 7 and 7a being in contact with the refractory metal layer 8 are modified to form silicide layers 9 and 9a having a thickness of not more than about 5 nm. The silicide layers 9 and 9a have an etch selectivity different from that of the refractory metal layer 8. Upon the subsequent removal of the refractory metal layer 8, accordingly, it is possible to prevent the silicide layers 9 and 9a from being etched together with the refractory metal layer 8, resulting in achieving a stabilized processing.
The second insulation layer pattern 5a is used as a channel passivation layer, whereas the portion of amorphous silicon layer 4 disposed beneath the second insulation layer pattern 5a is used as a channel layer. On the other hand, the N.sup.+ type conductive layers 7 and 7a formed at opposite sides of the second insulation pattern 5a are used as source and drain regions, respectively. The silicide layers 9 and 9a formed on the N.sup.+ type conductive layers 7 and 7a are used as source and drain electrodes, respectively.
Thereafter, the refractory metal layer 8 is subjected to a patterning using an etchant, so as to leave refractory metal layer portions 10 and 10a at opposite side ends of silicide layers 9 and 9a disposed at opposite sides of the second insulation pattern 5a, respectively, as shown in FIG. 3e.
As apparent from the above description, the technique by S. Nishida et al. makes it possible for source and drain regions to be formed above the gate electrode 2 in a self-aligned manner, according to the back substrate exposure process.
As a result, a channel overlap portion between the gate electrode and the source/drain regions is reduced so that the generation of parasitic capacitance between the gate electrode and the source/drain regions is considerably reduced, as compared with the technique using the lift-off process. Furthermore, it is possible to improve the signal-to-noise ratio, in that the parasitic capacitance acts as noise. According to the technique by S. Nishida et al., the channel overlap can be reduced to 1 .mu.m.
For obtaining a high quality of TFT-LCDS, it is most important that the channel overlap portion formed between the gate electrode and the source/drain regions is as small as possible. However, the technique by S. Nishida et al. encounters several problems as will be described hereinafter.
As shown in FIG. 3b, the photoresist pattern 6a which is formed by the back substrate exposure carried out at the back side of the transparent substrate 1 should have a width approximately equal to the length of the gate electrode 2. This width of photoresist pattern 6a makes it possible to reduce the channel overlap as much as possible. However, the actual width of photoresist pattern 6a is basically narrower than the length of gate electrode 2, as shown in FIG. 3b, due to a diffraction of the light which is used in the exposure process. As a result, channel overlap occurs at portions of the gate electrode 2 extending inwardly from its opposite side edges, respectively. Of course, the reduced width may vary slightly depending on the exposure time and the developing time.
In particular, the diffraction angle of the light (for example, g-line) used for the exposure is varied depending on thicknesses of the amorphous silicon layer 4, the first insulation layer 3 and the second insulation layer 5 formed on the transparent substrate 1. As a result, the widths of the photoresist pattern 6a and the second insulation layer pattern 5a are also varied. Due to these factors, the technique by S. Nishida et al. has a limitation on the reduction of channel overlap. Moreover, since the second insulation pattern 5a determines the extent of channel overlap as well as the widths of source and drain regions, frequent variation in the width of the second insulation layer pattern 5a causes the mass production of TFTs to be wanting in consistency, thereby resulting in several difficulties.
As apparent from the above description, there is a limitation on the reduction of channel overlap, in case of using only the self-alignment technique as proposed by S. Nishida et al.. Consequently, it is impossible to improve the characteristic of TFT.